The embodiments relate generally to a method for driving a phase change memory device, and more particularly, to a methodical technique of changing a write condition when an initial cell write characteristic is different so as to perform a normal write operation.
Some well known nonvolatile memory storage devices include magnetic memories and a phase change memories (PCM). The PCM components can exhibit data processing speeds similar to that of a volatile Random Access Memory (RAM) components. Further PCM components enjoy the advantage of being able to conserves data even after the power is turned off.
FIGS. 1a and 1b are diagrams illustrating a conventional phase change resistor (PCR) 4.
The conventional PCR 4 comprises a phase change material (PCM) 2 inserted between a top electrode 1 and a bottom electrode 3. When a voltage and a current are imposed across the top and bottom electrodes (1,3), the temperature is raised in the PCM 2 which results in altering the electric conductive properties and thereby the resistance changes as a function of the resultant solid state morphology. The PCM can include the chalcogenide, AgLnSbTe. The PCM 2 often times includes a chalcogenide having at least one of the chalcogen elements (S, Se, Te) as a main ingredient, and containing other ingredients such as, germanium and antimony. One PCM 2 of interest is the germanium antimonic tellurium consisting of Ge—Sb—Te (Ge2Sb2Te5).
FIGS. 2a and 2b are diagrams illustrating a principle of the conventional PCR 4.
As shown in FIG. 2a, the PCM 2 can maintain its crystalline morphology when a low current of less than a threshold value flows in the PCM 4. As a result, of the highly ordered crystalline morphology state of the PCM 2, the crystalline form of the PCM 2 exhibits a relatively low resistance.
As shown in FIG. 2b, the crystalline morphological state of the PCM 2 can be induced to melt when a current of more than a threshold value is imposed across the PCR 4. As a result of raising the temperature above the crystalline melting temperature coupled by relatively rapid cooling of the melted PCM 2, the solid state morphology of the PCM 2 can be transformed into an alternate solid state of being an amorphous morphology. Because of the increased number or increased density of crystal imperfections in these amorphous states, the amorphous PCM 2 exhibits a higher electrical resistance as compared to the PCM 2 in a crystalline state.
Accordingly, one can exploit this difference in physical properties by designing a PCR 4 to be configured to store nonvolatile data corresponding to the two resistance states. One could arbitrarily assign a data “1” state to refers to when the PCR 4 exhibits a relatively low resistance state. Likewise, one could arbitrarily assign a data “0” state to refer to when the PCR 4 exhibits a relatively high resistance state. Accordingly, binary logic states can be stored in these types of PCM devices without the need for powering these devices.
FIG. 3 is a diagram illustrating a write operation of a conventional phase change resistant cell.
When heat is generated from an electrical current flowing across the top electrode 1 and the bottom electrode 3 of the PCR 4, the solid state morphology of the PCM 2 can be transformed back and forth from a crystalline to an amorphous state when the heat is increased above the melting point.
In contrast, when heat is generated from a low amount of electrical current flowing across the top electrode 1 and the bottom electrode 3 of the PCR 4, the solid state morphology of the PCM 2 in the crystalline state can be maintained. As mentioned above, when the PCR 4 is in a crystalline state it exhibits a relatively lower resistance which can be arbitrarily defined to be a set state. On the other hand, when a high electrical current flows across the top electrode 1 and the bottom electrode 3 of the PCR 4, the PCM can be transformed into an amorphous state from the heating and from the rapid cooling. As a consequence when the PCR 4 is in the amorphous state it exhibits a relatively higher resistance which can be arbitrarily defined as a reset state. A physical property difference between these two morphological solid state phases is the responsible agent for the changes in the electric resistances.
A low voltage is applied to the PCR 4 for a long time in order to allow the PCM 2 to transform into the crystalline state and thus write the set state in a write mode. On the other hand, a high voltage is applied to the PCR 4 for a short time in order to allow the melted PCM 2 to rapidly cool into the amorphous state and thus write the reset state in the write mode.
FIG. 5 is a diagram illustrating cell characteristic distribution of a conventional phase change memory device.
Each cell includes in a plurality of cell arrays which has a different read current distribution because process, device and design conditions are different. That is, the distribution of a set current Iset and a reset current Ireset becomes broader based on a read current.
Based on a reference current Iref, read currents are overlapped with each other in a part of the cells. When the reset current Ireset and the set current Iset are distinguished by a reference current Iref, a fail condition occurs in a part of the cells.